H.264 Encoder Overview

Micro footprint low latency Encoder core

H.264 Encoder Overview

H.264 Encoder for FPGA's

H.264 ENCODER FPGA Core - High Speed Micro Footprint

Our FPGA core is highly optimized and 80% SMALLER AND FASTER THAN THE COMPETITION WITH ⟨ 1ms LATENCY @ 1080p30!


The A2e H.264 Encoder is capable of being synthesized in many FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 95Mhz. Typical clock rate in a Xilinx Zynq 7020 is 95MHz. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.


H.264 Encoder Features

  • 1.5 clocks/pixel processing rate
  • Fully compatible with the ITU-T H.264 specification
  • Available with bus widths from 8-12 to handle deeper pixel depths (Pre-compiled for Binary license.)
  • Supports resolutions up to 4096 x 4096 (can be expanded with additional cores)
  • Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
  • Generates I and P frames
  • Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
  • Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution
  • Entropy Encoding: CAVLC
  • Support for intra 4 x 4 DC prediction
  • Support for Single or Multiple slices via firmware control
  • Supports YUV 4:2:0 video input
  • Fully synchronous design
  • Available as FPGA specific netlist
  • Custom versions available

Recent Enhanced Features

  • New improved AXI wrapper to simplify integration of core
  • AXI stream for video input and compressed output
  • Latency reduced from 1 frame to less than 1ms for a 1080p30 video stream
  • LOWEST LATENCY IN THE INDUSTRY!
  • Others quote low latency but limit it to I frame only. Our core is low latency and supports I and P frames!
  • Significant reduction in Block RAM requirements for external raster to macroblock reordering

Additional Features

  • Xilinx AXI Bus Support

Deliverables

  • FPGA specific netlist
  • Bit accurate C model
  • Complete HDLtestbench
  • Test images
  • Complete data sheet

Licensing Options

  • Evaluation
  • Development
  • Project
  • Unlimited

AMD/Xilinx

  • Spartan
  • Artix
  • Kintex
  • UltraScale(+)
  • Zynq
  • Versal

MicroSemi

  • Igloo2
  • PolarFire

Why use an A2e H.264 Encoder FPGA Core vs DaVinci/iMx6?

Why A2e Table

Get the Data Sheet!

The Data Sheet contains more details on functionality and deliverables. Please email sales to learn more. (sales@A2eTechnologies.com

Pricing

Please contact us at sales@A2eTechnologies.com for pricing information and any other questions